The present disclosure relates generally to computer system clocking, and, in particular, to digitally controlled multi-frequency clocking of multi-core processors.
Computer systems, such as servers, have encountered technology limitations associated with scaling performance by continuing to increase processor clock frequency. An approach being exploited in the industry to alleviate this bottleneck is the use of multiple processors working in synchronism to achieve higher performance. It has been shown that the scaling of these configurations for commercial use is approximately linear (sub-linear) with the number of processors but continues to scale with large numbers of processors. To date, the technique has been demonstrated for small numbers of processors (e.g., less than 100) at modest frequencies (e.g., less than 5 GHz). This approach usually contains multiple processor chips which are interconnected together with a clocking and data fabric to insure a quasi-synchronous structure. Silicon technology density improvements from generation to generation have enabled the placement of multiple processor cores on a processor chip to further the scaling of this paradigm.
This new paradigm, however, requires the distribution of a common clock to all the processor chips and cores. The increasing difficulty and hardware cost, as well as signal integrity concerns, associated with the transmission of high frequency clocking throughout a multi-chip and multi-core processor computer system make this an untenable long-term strategy for future systems. The state of the art for clock distribution is based on analog signals using transmission lines. This technique is limited in scalability due to skin effect, media and connector loss, crosstalk, termination mismatches, and the like. Today's large servers contain, for example, greater than 10 processor chips typically containing two cores. It is expected that demand for both the number of processor chips and cores per chip will increase in the future. Transmission of high frequency clocks (>5-10 GHz) for multiple chips, with multiple cores, in server systems is not feasible with known board technology and connectors. Operating this configuration in a tightly coupled mode, as a symmetric multi-processor (SMP), will require a new clocking paradigm.
Additionally, as chips become larger with more cores, regional process and parameter variability across a chip due to fabrication may result in each core having an optimal power/performance metric at a different chip voltage and clock frequency setting. As the chips get larger, the variability between the cores will increase. Obtaining optimum performance for each core within a multi-core system is not feasible today. Separate core fixed voltage domains are known, but they can only serve to optimize the power at the chip level and not obtain optimum chip performance.
Therefore, it would be beneficial to develop an approach to provide general processor clocking for multiple multi-core processor chip computer systems. Such an approach would enable a multiple processor computer system, e.g., a server, to maintain clock signal integrity and optimal frequency performance of each core independently, as well as higher total performance at a given power level. Conversely, power optimization on a processor core basis would also be advantageous. Further extendibility, as more cores per chip and larger chips exacerbate high frequency clock tree structures and optimization problems, would provide additional benefits. Accordingly, there is a need in the art for digitally controlled multi-frequency clocking in multi-core processor systems.